In general, semiconductor memory devices generate internal voltages in response to a power supply voltage signal VDD and a ground voltage signal VSS, which are inputted from an external device, to use them in operations of internal circuits constituting the semiconductor memory devices. The internal voltages for operating the internal circuits of the semiconductor memory devices may include a core voltage VCORE for using in a memory core region, a high voltage VPP for word line drive or word line overdrive, and a back-bias voltage VBB applied to a bulk region (e.g., a substrate) of NMOS transistors in the memory core region.
The core voltage VCORE may be a positive voltage which is lower than the power supply voltage signal VDD supplied by the external device. Thus, the core voltage VCORE may be generated by lowering the power supply voltage signal VDD to a certain level. In contrast to the core voltage VCORE, the high voltage VPP may be higher than the power supply voltage signal VDD, and the back-bias voltage VBB may be a negative voltage which is lower than the ground voltage signal VSS. Thus, charge pump circuits may be required to generate the high voltage VPP and the back-bias voltage VBB.
The semiconductor memory devices may operate at a high speed by increasing a frequency of an external clock signal, and the use of the internal voltages may increase when the semiconductor memory devices operate at a high speed. Therefore, the semiconductor memory devices may be so designed as to activate many internal voltage generation circuits when the semiconductor memory devices operate at a high speed.
However, even when the semiconductor memory devices do not operate at a high speed, some internal voltage generation circuits, which are not required to operate, may be still activated, thereby increasing power consumption of the semiconductor memory devices.